The present invention relates generally to the fabrication of integrated circuits (ICs) and, in particular, to techniques for fabricating ICs such that the ICs suffer a reduced amount of plasma induced damage during plasma processing steps.
Integrated circuits that incorporate active elements such as metal-oxide-semiconductor (MOS) are fabricated from semiconductor wafers by using multiple steps to grow and deposit materials used in the integrated circuit. Such steps may include wafer fabrication, growth of oxide layers through thermal oxidation, ion implantation, doping, deposition of various insulating, conducting and semiconducting materials, deposition of various types photoresists, and lithography. One process used to deposit materials is chemical vapor deposition (CVD) in which a vapor is flowed over the surface on which a layer of material is to be deposited under conditions such that the vapor reacts with the surface to deposit the desired layer. The efficiency of CVD can be enhanced by flowing the vapor in the presence of a plasma that is used to create ions and radicals that recombine to deposit the desired layer on the surface. This technique is known as plasma enhanced CVD or PECVD.
In the process of preparing an IC, materials may be selectively removed from the IC at various times during its preparation. Techniques used to remove materials from the IC include wet etching, such as chemical etching or electrochemical etching, and dry etching, such as reactive ion etching (RIE) or other plasma etching techniques. During RIE a plasma is created and a voltage bias is created to direct ions from the plasma into the surface to be etched.
During IC fabrication, plasma processing may be used, for example, to selectively remove material from the surface of an IC in order to create a pattern of contact holes on the surface of the IC. The contact holes are filled, during later processing steps, with conductive material to establish contacts to the source, gate, and drain of the transistors on the IC. Generally, polysilicon (or titanium silicide, cobalt silicide, or platinum silicide over polysilicon) lies at the bottom of a contact hole used to make a contact to the gate of a transistor (gate contacts), and active silicon (or titanium silicide cobalt silicide, or platinum silicide over active silicon) lies at the bottom of a contact hole used to make a contact to a source or drain of a transistor (active contacts). Plasma processing is used to remove pre-metal dielectric material over the polysilicon gate contacts and the active silicon active contacts so that contacts may be established to the gate, source and drain of transistors on the IC.
During plasma processing, a plasma is created by ionizing a gas with a radio-frequency (RF) electromagnetic field. In typical plasma processes used in the semiconductor industry, the wafer on which the IC is created is backed by a blocking capacitor, such that direct current (DC) cannot pass through the wafer. Thus, the time average (over one RF cycle) electron flux to the wafer must match the time average ion flux to the wafer. Plasma physics requires, however, that the ions impacting the surface are highly directional, while the electrons are much less directional, and form a nearly isotropic cloud.
If an insulating surface, for example, photoresist or oxide, that is exposed to the plasma is not flat and smooth the ion and electron angular distributions are shadowed differently by the topology of the surface. In the case of contact holes, ions penetrate more effectively to the bottom of the contact holes and cause a positive potential to build up there. The resulting potential scales with the aspect ratio (depth divided by width) of the topology and with plasma parameters (for example, electron and ion angular and energy distributions) and can reach tens to hundreds of volts.
When contact holes are etched in an IC so that contacts can be made to the gate, source and drain of the transistors, the depth of the contact holes above active silicon (active contacts) are generally deeper than those to transistor gates (gate contacts). Thus, if the width of the gate and active contacts are equal, different potentials will be imposed upon these different circuit elements. Since gates and active circuit elements are connected by conducting materials except for a small thickness of insulating material, e.g. the thickness of the gate oxide, a strong electric field through the insulating material may result from the potential difference present during plasma processing at the bottoms of neighboring contact holes (i.e., active and gate contacts to the same transistor separated by the thickness of the gate oxide). This electric field may be strong enough to cause dielectric breakdown wherein the dielectric or insulating material becomes conducting. Dielectric breakdown may destroy the transistor or capacitor. In less extreme cases, the potential difference may cause Fowler-Nordheim tunneling of a current through the insulating material, which may cause bond rupture, the generation of defects such as vacancies, and interstitials, and other damage to the insulating material through which the current tunnels. The size of the damaged region may be comparable to the thickness of the gate oxide. Some of these defects are electrically charged and this may undesirably change the threshold voltage of the transistors.
After all plasma processing operations have been completed, an anneal containing hydrogen or deuterium containing is typically used to neutralize charged defects as much as possible. Nevertheless, the resulting hydrogen or deuterium passivated defect can be re-ionized by hot electron stressing. Thus, the damage to the IC may not be immediately apparent just subsequent to fabrication, but may appear only later during use, or in hot electron reliability studies of the IC.
Damage due to plasma processing according to the processes described above can also occur when neighboring contact holes are simultaneously etched to two plates of a capacitor structure and the contact holes have different depths and an identical width. In this case the potential difference is imposed across the capacitor dielectric. Dielectric breakdown of the capacitor dielectric can destroy the capacitor.
Damage due to the above described processes may occur during many different kinds of plasma processes, for example, plasma etching, reactive ion etching (RIE), magnetically enhanced reactive ion etching (MERIE), reactive sputter etching (RSE), high density plasma etching (HDP RIE), electron cyclotron resonance plasma etching (ECR RIE), helicon plasma etching, transformer coupled plasma etching (TCP RIE), inductively coupled plasma etching, decoupled plasma source reactive ion etching (DPS RIE) and reactive ion beam etching (RIBE). The common feature of these anisotropic etching processes (including the ion beam case where the beam itself is a quasi-neutral plasma whose electrons are usually supplied by an electron emission source near the beam) is that the positive ions are highly directional while the neutralizing flux of electrons is much less directional.
Although various techniques have been employed to repair plasma induced damage to the insulating material of the gate oxide portion of an IC a fabrication process that reduces or eliminates damage during the plasma processing stages is desirable.